// Copyright (C) 1953-2022 NUDT
// Verilog module name - tsnnic 
// Version:V4.1.0.20221213
// Created:
//         by - fenglin 
////////////////////////////////////////////////////////////////////////////
// Description:
//               
///////////////////////////////////////////////////////////////////////////

`timescale 1ns/1ps

module tsnnic
(
       i_clk,
       
       i_hard_rst_n,
       i_button_rst_n,
       i_et_resetc_rst_n, 

       i_gmii_rxclk_p0,
       i_gmii_dv_p0,
       iv_gmii_rxd_p0,
       i_gmii_er_p0,	   
       
       ov_gmii_txd_p0,
       o_gmii_tx_en_p0,
       o_gmii_tx_er_p0,
       o_gmii_tx_clk_p0,
	   
	   iv_data_host,
	   i_data_wr_host,

	   ov_data_host,
	   o_data_wr_host,
       //i_gmii_rxclk_p1,
       //i_gmii_dv_p1,
       //iv_gmii_rxd_p1,
       //i_gmii_er_p1,
	   //
       //ov_gmii_txd_p1,
       //o_gmii_tx_en_p1,
       //o_gmii_tx_er_p1,
       //o_gmii_tx_clk_p1,
       //
	   //
       //i_gmii_rxclk_p2,
       //i_gmii_dv_p2,
       //iv_gmii_rxd_p2,
       //i_gmii_er_p2,
	   //
       //ov_gmii_txd_p2,
       //o_gmii_tx_en_p2,
       //o_gmii_tx_er_p2,
       //o_gmii_tx_clk_p2,
       //
       //i_gmii_rxclk_p3,
       //i_gmii_dv_p3,
       //iv_gmii_rxd_p3,
       //i_gmii_er_p3,
	   //
       //ov_gmii_txd_p3,
       //o_gmii_tx_en_p3,
       //o_gmii_tx_er_p3,
       //o_gmii_tx_clk_p3,
	   
       reset_clk_pulse,
       ov_hardware_stage,
	   o_s_pulse        ,
       o_cyclestart,
       o_sync_ok   ,
       ov_syn_clk	   
);

input                   i_clk;                  //125Mhz

input                   i_hard_rst_n;
input                   i_button_rst_n;
input                   i_et_resetc_rst_n;

output                  reset_clk_pulse;
output                  o_cyclestart;
output                  o_sync_ok; 
//input
input                   i_gmii_rxclk_p0;
input                   i_gmii_dv_p0;
input       [7:0]       iv_gmii_rxd_p0;
input                   i_gmii_er_p0;

//input                   i_gmii_rxclk_p1;
//input                   i_gmii_dv_p1;
//input       [7:0]       iv_gmii_rxd_p1;
//input                   i_gmii_er_p1;
//
//input                   i_gmii_rxclk_p2;
//input                   i_gmii_dv_p2;
//input       [7:0]       iv_gmii_rxd_p2;
//input                   i_gmii_er_p2;
//
//input                   i_gmii_rxclk_p3;
//input                   i_gmii_dv_p3;
//input       [7:0]       iv_gmii_rxd_p3;
//input                   i_gmii_er_p3;
//output
output      [7:0]       ov_gmii_txd_p0;
output                  o_gmii_tx_en_p0;
output                  o_gmii_tx_er_p0;
output                  o_gmii_tx_clk_p0;

//output      [7:0]       ov_gmii_txd_p1;
//output                  o_gmii_tx_en_p1;
//output                  o_gmii_tx_er_p1;
//output                  o_gmii_tx_clk_p1;
//
//output      [7:0]       ov_gmii_txd_p2;
//output                  o_gmii_tx_en_p2;
//output                  o_gmii_tx_er_p2;
//output                  o_gmii_tx_clk_p2;
//
//output      [7:0]       ov_gmii_txd_p3;
//output                  o_gmii_tx_en_p3;
//output                  o_gmii_tx_er_p3;
//output                  o_gmii_tx_clk_p3;

input       [8:0]       iv_data_host;
input                   i_data_wr_host;

output      [8:0]       ov_data_host;
output                  o_data_wr_host;

output      [2:0]       ov_hardware_stage;
output  reg             o_s_pulse        ;

wire        [11:0]      wv_hcp_mid_hcp2tse                    ;
wire        [31:0]      wv_tse_ver_tse2hcp                    ;
wire                    w_rc_rxenable_hcp2tss                 ;
wire                    w_st_rxenable_hcp2tss                 ;
wire                    w_tsmp_lookup_table_key_wr_tse2hcp    ;
wire        [47:0]      wv_tsmp_lookup_table_key_tse2hcp      ;
wire        [32:0]      wv_tsmp_lookup_table_outport_hcp2tse  ;
wire                    w_tsmp_lookup_table_outport_wr_hcp2tse;

wire        [65:0]      wv_command_hcp2hub        ;   
wire                    w_command_wr_hcp2hub      ; 
wire        [65:0]      wv_command_ack_hub2hcp    ;
wire                    w_command_ack_wr_hub2hcp  ; 

wire        [63:0]      wv_command_hub2tse        ;  
wire                    w_command_wr_hub2tse      ;
wire        [63:0]      wv_command_tse2hub        ;
wire                    w_command_wr_tse2hub      ;

wire        [63:0]      wv_command_frer2hub       ;
wire                    w_command_wr_frer2hub     ;
wire        [63:0]      wv_command_hub2frer       ;
wire                    w_command_wr_hub2frer     ;

wire        [63:0]      wv_command_hub2tau        ;
wire                    w_command_wr_hub2tau      ;
wire        [63:0]      wv_command_tau2hub        ;
wire                    w_command_wr_tau2hub      ;

wire        [63:0]      wv_command_hub2osm_0      ;
wire                    w_command_wr_hub2osm_0    ;
wire        [63:0]      wv_command_osm2hub_0      ;
wire                    w_command_wr_osm2hub_0    ;

wire        [63:0]      wv_command_hub2osm_1      ;
wire                    w_command_wr_hub2osm_1    ;
wire        [63:0]      wv_command_osm2hub_1      ;
wire                    w_command_wr_osm2hub_1    ;

wire        [63:0]      wv_command_hub2osm_2      ;
wire                    w_command_wr_hub2osm_2    ;
wire        [63:0]      wv_command_osm2hub_2      ;
wire                    w_command_wr_osm2hub_2    ;

wire        [63:0]      wv_command_hub2osm_3      ;
wire                    w_command_wr_hub2osm_3    ;
wire        [63:0]      wv_command_osm2hub_3      ;
wire                    w_command_wr_osm2hub_3    ;

wire        [63:0]      wv_command_hub2osm_4      ;
wire                    w_command_wr_hub2osm_4    ;
wire        [63:0]      wv_command_osm2hub_4      ;
wire                    w_command_wr_osm2hub_4    ;

wire        [63:0]      wv_command_hub2osm_5      ;
wire                    w_command_wr_hub2osm_5    ;
wire        [63:0]      wv_command_osm2hub_5      ;
wire                    w_command_wr_osm2hub_5    ;

wire        [63:0]      wv_command_hub2osm_6      ;
wire                    w_command_wr_hub2osm_6    ;
wire        [63:0]      wv_command_osm2hub_6      ;
wire                    w_command_wr_osm2hub_6    ;

wire        [63:0]      wv_command_hub2osm_7      ;
wire                    w_command_wr_hub2osm_7    ;
wire        [63:0]      wv_command_osm2hub_7      ;
wire                    w_command_wr_osm2hub_7    ;

//wire        [79:0]      wv_syn_clk_stc2swc   ;
output      [79:0]      ov_syn_clk;
wire                    w_local_cnt_rst_hcp2osm;
//adp2tsnchip 
/*
wire                    w_data_wr_p0_tse2osm;
wire        [8:0]       wv_data_p0_tse2osm  ;
wire                    w_data_ready_p0_osm2tse;
wire                    w_data_wr_p0_osm2tse;
wire        [8:0]       wv_data_p0_osm2tse  ;

wire                    w_data_wr_p1_tse2osm;
wire        [8:0]       wv_data_p1_tse2osm  ;
wire                    w_data_ready_p1_osm2tse;
wire                    w_data_wr_p1_osm2tse;
wire        [8:0]       wv_data_p1_osm2tse  ;

wire                    w_data_wr_p2_tse2osm;
wire        [8:0]       wv_data_p2_tse2osm  ;
wire                    w_data_ready_p2_osm2tse;
wire                    w_data_wr_p2_osm2tse;
wire        [8:0]       wv_data_p2_osm2tse  ;
*/
wire                    w_data_wr_p0_frer2osm;
wire        [8:0]       wv_data_p0_frer2osm  ;
wire                    w_data_ready_p0_osm2frer;
wire                    w_data_wr_p0_osm2frer;
wire        [8:0]       wv_data_p0_osm2frer  ;

wire                    w_data_wr_p1_frer2osm;
wire        [8:0]       wv_data_p1_frer2osm  ;
wire                    w_data_ready_p1_osm2frer;
wire                    w_data_wr_p1_osm2frer;
wire        [8:0]       wv_data_p1_osm2frer  ;

wire                    w_data_wr_p2_frer2osm;
wire        [8:0]       wv_data_p2_frer2osm  ;
wire                    w_data_ready_p2_osm2frer;
wire                    w_data_wr_p2_osm2frer;
wire        [8:0]       wv_data_p2_osm2frer  ;

wire                    w_data_wr_p3_tse2osm;
wire        [8:0]       wv_data_p3_tse2osm  ;
wire                    w_data_ready_p3_osm2tse;
wire                    w_data_wr_p3_osm2tse;
wire        [8:0]       wv_data_p3_osm2tse  ;

wire                    w_data_wr_frer2tse    ;
wire        [8:0]       wv_data_frer2tse      ;
wire                    w_data_ready_frer2tse ;
wire                    w_data_wr_tse2frer    ;
wire        [8:0]       wv_data_tse2frer      ;

wire                    w_data_wr_hcp2tse              ;
wire        [8:0]       wv_data_hcp2tse                ;

wire        [8:0]       wv_data_tse2hcp                ;
wire                    w_data_wr_tse2hcp           ;     

wire                    w_tsn_or_tte_hcp2osm           ;

wire                    w_osm_req_tx_pulse_p0_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p0_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p1_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p1_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p2_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p2_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p3_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p3_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p4_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p4_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p5_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p5_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p6_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p6_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p7_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p7_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p8_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p8_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p9_osm2hcp   ;
wire                    w_osm_resp_rx_pulse_p9_osm2hcp  ;
wire                    w_osm_req_tx_pulse_p10_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p10_osm2hcp ;
wire                    w_osm_req_tx_pulse_p11_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p11_osm2hcp ;
wire                    w_osm_req_tx_pulse_p12_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p12_osm2hcp ;
wire                    w_osm_req_tx_pulse_p13_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p13_osm2hcp ;
wire                    w_osm_req_tx_pulse_p14_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p14_osm2hcp ;
wire                    w_osm_req_tx_pulse_p15_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p15_osm2hcp ;
wire                    w_osm_req_tx_pulse_p16_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p16_osm2hcp ;
wire                    w_osm_req_tx_pulse_p17_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p17_osm2hcp ;
wire                    w_osm_req_tx_pulse_p18_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p18_osm2hcp ;
wire                    w_osm_req_tx_pulse_p19_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p19_osm2hcp ;
wire                    w_osm_req_tx_pulse_p20_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p20_osm2hcp ;
wire                    w_osm_req_tx_pulse_p21_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p21_osm2hcp ;
wire                    w_osm_req_tx_pulse_p22_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p22_osm2hcp ;
wire                    w_osm_req_tx_pulse_p23_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p23_osm2hcp ;
wire                    w_osm_req_tx_pulse_p24_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p24_osm2hcp ;
wire                    w_osm_req_tx_pulse_p25_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p25_osm2hcp ;
wire                    w_osm_req_tx_pulse_p26_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p26_osm2hcp ;
wire                    w_osm_req_tx_pulse_p27_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p27_osm2hcp ;
wire                    w_osm_req_tx_pulse_p28_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p28_osm2hcp ;
wire                    w_osm_req_tx_pulse_p29_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p29_osm2hcp ;
wire                    w_osm_req_tx_pulse_p30_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p30_osm2hcp ;
wire                    w_osm_req_tx_pulse_p31_osm2hcp  ;
wire                    w_osm_resp_rx_pulse_p31_osm2hcp ;

wire                    w_osm_req_rx_pulse_p0_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p0_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p1_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p1_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p2_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p2_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p3_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p3_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p4_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p4_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p5_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p5_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p6_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p6_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p7_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p7_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p8_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p8_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p9_osm2hcp   ;
wire                    w_osm_resp_tx_pulse_p9_osm2hcp  ;
wire                    w_osm_req_rx_pulse_p10_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p10_osm2hcp ;
wire                    w_osm_req_rx_pulse_p11_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p11_osm2hcp ;
wire                    w_osm_req_rx_pulse_p12_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p12_osm2hcp ;
wire                    w_osm_req_rx_pulse_p13_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p13_osm2hcp ;
wire                    w_osm_req_rx_pulse_p14_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p14_osm2hcp ;
wire                    w_osm_req_rx_pulse_p15_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p15_osm2hcp ;
wire                    w_osm_req_rx_pulse_p16_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p16_osm2hcp ;
wire                    w_osm_req_rx_pulse_p17_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p17_osm2hcp ;
wire                    w_osm_req_rx_pulse_p18_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p18_osm2hcp ;
wire                    w_osm_req_rx_pulse_p19_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p19_osm2hcp ;
wire                    w_osm_req_rx_pulse_p20_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p20_osm2hcp ;
wire                    w_osm_req_rx_pulse_p21_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p21_osm2hcp ;
wire                    w_osm_req_rx_pulse_p22_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p22_osm2hcp ;
wire                    w_osm_req_rx_pulse_p23_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p23_osm2hcp ;
wire                    w_osm_req_rx_pulse_p24_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p24_osm2hcp ;
wire                    w_osm_req_rx_pulse_p25_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p25_osm2hcp ;
wire                    w_osm_req_rx_pulse_p26_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p26_osm2hcp ;
wire                    w_osm_req_rx_pulse_p27_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p27_osm2hcp ;
wire                    w_osm_req_rx_pulse_p28_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p28_osm2hcp ;
wire                    w_osm_req_rx_pulse_p29_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p29_osm2hcp ;
wire                    w_osm_req_rx_pulse_p30_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p30_osm2hcp ;
wire                    w_osm_req_rx_pulse_p31_osm2hcp  ;
wire                    w_osm_resp_tx_pulse_p31_osm2hcp ;
//reset sync
wire                    w_core_rst_n;
wire                    w_gmii_rst_n_p0;
wire                    w_gmii_rst_n_p1;
wire                    w_gmii_rst_n_p2;
wire                    w_gmii_rst_n_p3;
wire                    w_gmii_rst_n_p4;
wire                    w_gmii_rst_n_p5;
wire                    w_gmii_rst_n_p6;
wire                    w_gmii_rst_n_p7;
wire                    w_gmii_rst_n_p8;
                        
wire                    w_rst_n;

assign w_rst_n = i_hard_rst_n & i_button_rst_n & i_et_resetc_rst_n;
assign o_gmii_tx_clk_p0 = i_gmii_rxclk_p0;
//assign o_gmii_tx_clk_p1 = i_gmii_rxclk_p1;
//assign o_gmii_tx_clk_p2 = i_gmii_rxclk_p2;
//assign o_gmii_tx_clk_p3 = i_gmii_rxclk_p3;
//assign o_gmii_tx_clk_p4 = i_gmii_rxclk_p4;
//assign o_gmii_tx_clk_p5 = i_gmii_rxclk_p5;
//assign o_gmii_tx_clk_p6 = i_gmii_rxclk_p6;
//assign o_gmii_tx_clk_p7 = i_gmii_rxclk_p7;

assign ov_hardware_stage = {1'b0,w_st_rxenable_hcp2tss,w_rc_rxenable_hcp2tss};

reg   r_s_data;
always@(posedge i_clk or negedge w_core_rst_n)begin 
    if(!w_core_rst_n) begin
		o_s_pulse          <= 1'b0;
		r_s_data           <= 1'b0;
    end
    else begin
	    //r_s_data <= wv_syn_clk_stc2swc[32];
		r_s_data <= ov_syn_clk[32];
	    //if(r_s_data != wv_syn_clk_stc2swc[32])begin
		if(r_s_data != ov_syn_clk[32])begin
            o_s_pulse          <= 1'b1;
        end	
        else begin
            o_s_pulse          <= 1'b0;
        end		
	end
end
hardware_control_point hardware_control_point_inst
(
.i_clk                            (i_clk                     ),
.i_rst_n                          (w_core_rst_n              ),  

.i_tsnnic_or_tsnswitch            (1'b1                      ),//1:tsnnic.  0:tsnswitch
.ov_localclk                      (ov_syn_clk),//(wv_syn_clk_stc2swc        ),
.o_local_cnt_rst                  (w_local_cnt_rst_hcp2osm   ),     
.o_tsn_or_tte                     (w_tsn_or_tte_hcp2osm      ),

.i_data_wr_from_tss               (w_data_wr_tse2hcp         ),
.iv_data_from_tss                 (wv_data_tse2hcp           ),  
.ov_data_to_tss                   (wv_data_hcp2tse           ),
.o_data_wr_to_tss                 (w_data_wr_hcp2tse         ),

.i_gmii_rx_clk                      (i_clk),
.i_gmii_rx_dv                       (1'b0 ),
.iv_gmii_rxd                        (8'b0 ),
.i_gmii_rx_er                       (1'b0 ),
.o_gmii_tx_clk                      (),
.o_gmii_tx_en                       (),
.ov_gmii_txd                        (),
.o_gmii_tx_er                       (),

.ov_local_id                      (wv_hcp_mid_hcp2tse                    ), 
.iv_tss_ver                       (wv_tse_ver_tse2hcp                    ), 
.o_rc_rxenable                    (w_rc_rxenable_hcp2tss                 ), 
.o_st_rxenable                    (w_st_rxenable_hcp2tss                 ),
 
.i_tsmp_lookup_table_key_wr       (1'b0       ),
.iv_tsmp_lookup_table_key         (48'b0      ),
.ov_tsmp_lookup_table_outport     (wv_tsmp_lookup_table_outport_hcp2tse  ),
.o_tsmp_lookup_table_outport_wr   (w_tsmp_lookup_table_outport_wr_hcp2tse),

.o_cyclestart                    (o_cyclestart                         ),
.o_sync_ok                        (o_sync_ok                             ),

.ov_command_tss                   (wv_command_hub2tse  ),//(wv_command_hcp2hub                    ),
.o_command_wr_tss                 (w_command_wr_hub2tse),//(w_command_wr_hcp2hub                  ),        
.iv_command_ack_tss               (wv_command_tse2hub  ),//(wv_command_ack_hub2hcp                ),
.i_command_ack_wr_tss             (w_command_wr_tse2hub),//(w_command_ack_wr_hub2hcp              ),

.i_osm_req_tx_pulse_p0            (w_osm_req_tx_pulse_p0_osm2hcp  ),     
.i_osm_resp_rx_pulse_p0           (w_osm_resp_rx_pulse_p0_osm2hcp ),     
.i_osm_req_tx_pulse_p1            (1'b0),//(w_osm_req_tx_pulse_p1_osm2hcp  ),     
.i_osm_resp_rx_pulse_p1           (1'b0),//(w_osm_resp_rx_pulse_p1_osm2hcp ),     
.i_osm_req_tx_pulse_p2            (1'b0),//(w_osm_req_tx_pulse_p2_osm2hcp  ),     
.i_osm_resp_rx_pulse_p2           (1'b0),//(w_osm_resp_rx_pulse_p2_osm2hcp ),     
.i_osm_req_tx_pulse_p3            (1'b0),//(w_osm_req_tx_pulse_p3_osm2hcp  ),     
.i_osm_resp_rx_pulse_p3           (1'b0),//(w_osm_resp_rx_pulse_p3_osm2hcp ),     
.i_osm_req_tx_pulse_p4            (1'b0),//(w_osm_req_tx_pulse_p4_osm2hcp  ),     
.i_osm_resp_rx_pulse_p4           (1'b0),//(w_osm_resp_rx_pulse_p4_osm2hcp ),     
.i_osm_req_tx_pulse_p5            (1'b0),//(w_osm_req_tx_pulse_p5_osm2hcp  ),     
.i_osm_resp_rx_pulse_p5           (1'b0),//(w_osm_resp_rx_pulse_p5_osm2hcp ),     
.i_osm_req_tx_pulse_p6            (1'b0),//(w_osm_req_tx_pulse_p6_osm2hcp  ),     
.i_osm_resp_rx_pulse_p6           (1'b0),//(w_osm_resp_rx_pulse_p6_osm2hcp ),     
.i_osm_req_tx_pulse_p7            (1'b0),//(w_osm_req_tx_pulse_p7_osm2hcp  ),     
.i_osm_resp_rx_pulse_p7           (1'b0),//(w_osm_resp_rx_pulse_p7_osm2hcp ),     
.i_osm_req_tx_pulse_p8            (1'b0),//(w_osm_req_tx_pulse_p8_osm2hcp  ),     
.i_osm_resp_rx_pulse_p8           (1'b0),//(w_osm_resp_rx_pulse_p8_osm2hcp ),     
.i_osm_req_tx_pulse_p9            (1'b0),//(w_osm_req_tx_pulse_p9_osm2hcp  ),     
.i_osm_resp_rx_pulse_p9           (1'b0),//(w_osm_resp_rx_pulse_p9_osm2hcp ),     
.i_osm_req_tx_pulse_p10           (1'b0),//(w_osm_req_tx_pulse_p10_osm2hcp ),     
.i_osm_resp_rx_pulse_p10          (1'b0),//(w_osm_resp_rx_pulse_p10_osm2hcp),     
.i_osm_req_tx_pulse_p11           (1'b0),//(w_osm_req_tx_pulse_p11_osm2hcp ),     
.i_osm_resp_rx_pulse_p11          (1'b0),//(w_osm_resp_rx_pulse_p11_osm2hcp),     
.i_osm_req_tx_pulse_p12           (1'b0),//(w_osm_req_tx_pulse_p12_osm2hcp ),     
.i_osm_resp_rx_pulse_p12          (1'b0),//(w_osm_resp_rx_pulse_p12_osm2hcp),     
.i_osm_req_tx_pulse_p13           (1'b0),//(w_osm_req_tx_pulse_p13_osm2hcp ),     
.i_osm_resp_rx_pulse_p13          (1'b0),//(w_osm_resp_rx_pulse_p13_osm2hcp),     
.i_osm_req_tx_pulse_p14           (1'b0),//(w_osm_req_tx_pulse_p14_osm2hcp ),     
.i_osm_resp_rx_pulse_p14          (1'b0),//(w_osm_resp_rx_pulse_p14_osm2hcp),     
.i_osm_req_tx_pulse_p15           (1'b0),//(w_osm_req_tx_pulse_p15_osm2hcp ),     
.i_osm_resp_rx_pulse_p15          (1'b0),//(w_osm_resp_rx_pulse_p15_osm2hcp),     
.i_osm_req_tx_pulse_p16           (1'b0),//(w_osm_req_tx_pulse_p16_osm2hcp ),     
.i_osm_resp_rx_pulse_p16          (1'b0),//(w_osm_resp_rx_pulse_p16_osm2hcp),     
.i_osm_req_tx_pulse_p17           (1'b0),//(w_osm_req_tx_pulse_p17_osm2hcp ),     
.i_osm_resp_rx_pulse_p17          (1'b0),//(w_osm_resp_rx_pulse_p17_osm2hcp),     
.i_osm_req_tx_pulse_p18           (1'b0),//(w_osm_req_tx_pulse_p18_osm2hcp ),     
.i_osm_resp_rx_pulse_p18          (1'b0),//(w_osm_resp_rx_pulse_p18_osm2hcp),     
.i_osm_req_tx_pulse_p19           (1'b0),//(w_osm_req_tx_pulse_p19_osm2hcp ),     
.i_osm_resp_rx_pulse_p19          (1'b0),//(w_osm_resp_rx_pulse_p19_osm2hcp),     
.i_osm_req_tx_pulse_p20           (1'b0),//(w_osm_req_tx_pulse_p20_osm2hcp ),     
.i_osm_resp_rx_pulse_p20          (1'b0),//(w_osm_resp_rx_pulse_p20_osm2hcp),     
.i_osm_req_tx_pulse_p21           (1'b0),//(w_osm_req_tx_pulse_p21_osm2hcp ),     
.i_osm_resp_rx_pulse_p21          (1'b0),//(w_osm_resp_rx_pulse_p21_osm2hcp),     
.i_osm_req_tx_pulse_p22           (1'b0),//(w_osm_req_tx_pulse_p22_osm2hcp ),     
.i_osm_resp_rx_pulse_p22          (1'b0),//(w_osm_resp_rx_pulse_p22_osm2hcp),     
.i_osm_req_tx_pulse_p23           (1'b0),//(w_osm_req_tx_pulse_p23_osm2hcp ),     
.i_osm_resp_rx_pulse_p23          (1'b0),//(w_osm_resp_rx_pulse_p23_osm2hcp),     
.i_osm_req_tx_pulse_p24           (1'b0),//(w_osm_req_tx_pulse_p24_osm2hcp ),     
.i_osm_resp_rx_pulse_p24          (1'b0),//(w_osm_resp_rx_pulse_p24_osm2hcp),     
.i_osm_req_tx_pulse_p25           (1'b0),//(w_osm_req_tx_pulse_p25_osm2hcp ),     
.i_osm_resp_rx_pulse_p25          (1'b0),//(w_osm_resp_rx_pulse_p25_osm2hcp),     
.i_osm_req_tx_pulse_p26           (1'b0),//(w_osm_req_tx_pulse_p26_osm2hcp ),     
.i_osm_resp_rx_pulse_p26          (1'b0),//(w_osm_resp_rx_pulse_p26_osm2hcp),     
.i_osm_req_tx_pulse_p27           (1'b0),//(w_osm_req_tx_pulse_p27_osm2hcp ),     
.i_osm_resp_rx_pulse_p27          (1'b0),//(w_osm_resp_rx_pulse_p27_osm2hcp),     
.i_osm_req_tx_pulse_p28           (1'b0),//(w_osm_req_tx_pulse_p28_osm2hcp ),     
.i_osm_resp_rx_pulse_p28          (1'b0),//(w_osm_resp_rx_pulse_p28_osm2hcp),     
.i_osm_req_tx_pulse_p29           (1'b0),//(w_osm_req_tx_pulse_p29_osm2hcp ),     
.i_osm_resp_rx_pulse_p29          (1'b0),//(w_osm_resp_rx_pulse_p29_osm2hcp),     
.i_osm_req_tx_pulse_p30           (1'b0),//(w_osm_req_tx_pulse_p30_osm2hcp ),     
.i_osm_resp_rx_pulse_p30          (1'b0),//(w_osm_resp_rx_pulse_p30_osm2hcp),     
.i_osm_req_tx_pulse_p31           (1'b0),//(w_osm_req_tx_pulse_p31_osm2hcp ),     
.i_osm_resp_rx_pulse_p31          (1'b0),//(w_osm_resp_rx_pulse_p31_osm2hcp), 
                              
.i_osm_req_rx_pulse_p0            (w_osm_req_rx_pulse_p0_osm2hcp  ),
.i_osm_resp_tx_pulse_p0           (w_osm_resp_tx_pulse_p0_osm2hcp ),
.i_osm_req_rx_pulse_p1            (1'b0),//(w_osm_req_rx_pulse_p1_osm2hcp  ),
.i_osm_resp_tx_pulse_p1           (1'b0),//(w_osm_resp_tx_pulse_p1_osm2hcp ),
.i_osm_req_rx_pulse_p2            (1'b0),//(w_osm_req_rx_pulse_p2_osm2hcp  ),
.i_osm_resp_tx_pulse_p2           (1'b0),//(w_osm_resp_tx_pulse_p2_osm2hcp ),
.i_osm_req_rx_pulse_p3            (1'b0),//(w_osm_req_rx_pulse_p3_osm2hcp  ),
.i_osm_resp_tx_pulse_p3           (1'b0),//(w_osm_resp_tx_pulse_p3_osm2hcp ),
.i_osm_req_rx_pulse_p4            (1'b0),//(w_osm_req_rx_pulse_p4_osm2hcp  ),
.i_osm_resp_tx_pulse_p4           (1'b0),//(w_osm_resp_tx_pulse_p4_osm2hcp ),
.i_osm_req_rx_pulse_p5            (1'b0),//(w_osm_req_rx_pulse_p5_osm2hcp  ),
.i_osm_resp_tx_pulse_p5           (1'b0),//(w_osm_resp_tx_pulse_p5_osm2hcp ),
.i_osm_req_rx_pulse_p6            (1'b0),//(w_osm_req_rx_pulse_p6_osm2hcp  ),
.i_osm_resp_tx_pulse_p6           (1'b0),//(w_osm_resp_tx_pulse_p6_osm2hcp ),
.i_osm_req_rx_pulse_p7            (1'b0),//(w_osm_req_rx_pulse_p7_osm2hcp  ),
.i_osm_resp_tx_pulse_p7           (1'b0),//(w_osm_resp_tx_pulse_p7_osm2hcp ),
.i_osm_req_rx_pulse_p8            (1'b0),//(w_osm_req_rx_pulse_p8_osm2hcp  ),
.i_osm_resp_tx_pulse_p8           (1'b0),//(w_osm_resp_tx_pulse_p8_osm2hcp ),
.i_osm_req_rx_pulse_p9            (1'b0),//(w_osm_req_rx_pulse_p9_osm2hcp  ),
.i_osm_resp_tx_pulse_p9           (1'b0),//(w_osm_resp_tx_pulse_p9_osm2hcp ),
.i_osm_req_rx_pulse_p10           (1'b0),//(w_osm_req_rx_pulse_p10_osm2hcp ),
.i_osm_resp_tx_pulse_p10          (1'b0),//(w_osm_resp_tx_pulse_p10_osm2hcp),
.i_osm_req_rx_pulse_p11           (1'b0),//(w_osm_req_rx_pulse_p11_osm2hcp ),
.i_osm_resp_tx_pulse_p11          (1'b0),//(w_osm_resp_tx_pulse_p11_osm2hcp),
.i_osm_req_rx_pulse_p12           (1'b0),//(w_osm_req_rx_pulse_p12_osm2hcp ),
.i_osm_resp_tx_pulse_p12          (1'b0),//(w_osm_resp_tx_pulse_p12_osm2hcp),
.i_osm_req_rx_pulse_p13           (1'b0),//(w_osm_req_rx_pulse_p13_osm2hcp ),
.i_osm_resp_tx_pulse_p13          (1'b0),//(w_osm_resp_tx_pulse_p13_osm2hcp),
.i_osm_req_rx_pulse_p14           (1'b0),//(w_osm_req_rx_pulse_p14_osm2hcp ),
.i_osm_resp_tx_pulse_p14          (1'b0),//(w_osm_resp_tx_pulse_p14_osm2hcp),
.i_osm_req_rx_pulse_p15           (1'b0),//(w_osm_req_rx_pulse_p15_osm2hcp ),
.i_osm_resp_tx_pulse_p15          (1'b0),//(w_osm_resp_tx_pulse_p15_osm2hcp),
.i_osm_req_rx_pulse_p16           (1'b0),//(w_osm_req_rx_pulse_p16_osm2hcp ),
.i_osm_resp_tx_pulse_p16          (1'b0),//(w_osm_resp_tx_pulse_p16_osm2hcp),
.i_osm_req_rx_pulse_p17           (1'b0),//(w_osm_req_rx_pulse_p17_osm2hcp ),
.i_osm_resp_tx_pulse_p17          (1'b0),//(w_osm_resp_tx_pulse_p17_osm2hcp),
.i_osm_req_rx_pulse_p18           (1'b0),//(w_osm_req_rx_pulse_p18_osm2hcp ),
.i_osm_resp_tx_pulse_p18          (1'b0),//(w_osm_resp_tx_pulse_p18_osm2hcp),
.i_osm_req_rx_pulse_p19           (1'b0),//(w_osm_req_rx_pulse_p19_osm2hcp ),
.i_osm_resp_tx_pulse_p19          (1'b0),//(w_osm_resp_tx_pulse_p19_osm2hcp),
.i_osm_req_rx_pulse_p20           (1'b0),//(w_osm_req_rx_pulse_p20_osm2hcp ),
.i_osm_resp_tx_pulse_p20          (1'b0),//(w_osm_resp_tx_pulse_p20_osm2hcp),
.i_osm_req_rx_pulse_p21           (1'b0),//(w_osm_req_rx_pulse_p21_osm2hcp ),
.i_osm_resp_tx_pulse_p21          (1'b0),//(w_osm_resp_tx_pulse_p21_osm2hcp),
.i_osm_req_rx_pulse_p22           (1'b0),//(w_osm_req_rx_pulse_p22_osm2hcp ),
.i_osm_resp_tx_pulse_p22          (1'b0),//(w_osm_resp_tx_pulse_p22_osm2hcp),
.i_osm_req_rx_pulse_p23           (1'b0),//(w_osm_req_rx_pulse_p23_osm2hcp ),
.i_osm_resp_tx_pulse_p23          (1'b0),//(w_osm_resp_tx_pulse_p23_osm2hcp),
.i_osm_req_rx_pulse_p24           (1'b0),//(w_osm_req_rx_pulse_p24_osm2hcp ),
.i_osm_resp_tx_pulse_p24          (1'b0),//(w_osm_resp_tx_pulse_p24_osm2hcp),
.i_osm_req_rx_pulse_p25           (1'b0),//(w_osm_req_rx_pulse_p25_osm2hcp ),
.i_osm_resp_tx_pulse_p25          (1'b0),//(w_osm_resp_tx_pulse_p25_osm2hcp),
.i_osm_req_rx_pulse_p26           (1'b0),//(w_osm_req_rx_pulse_p26_osm2hcp ),
.i_osm_resp_tx_pulse_p26          (1'b0),//(w_osm_resp_tx_pulse_p26_osm2hcp),
.i_osm_req_rx_pulse_p27           (1'b0),//(w_osm_req_rx_pulse_p27_osm2hcp ),
.i_osm_resp_tx_pulse_p27          (1'b0),//(w_osm_resp_tx_pulse_p27_osm2hcp),
.i_osm_req_rx_pulse_p28           (1'b0),//(w_osm_req_rx_pulse_p28_osm2hcp ),
.i_osm_resp_tx_pulse_p28          (1'b0),//(w_osm_resp_tx_pulse_p28_osm2hcp),
.i_osm_req_rx_pulse_p29           (1'b0),//(w_osm_req_rx_pulse_p29_osm2hcp ),
.i_osm_resp_tx_pulse_p29          (1'b0),//(w_osm_resp_tx_pulse_p29_osm2hcp),
.i_osm_req_rx_pulse_p30           (1'b0),//(w_osm_req_rx_pulse_p30_osm2hcp ),
.i_osm_resp_tx_pulse_p30          (1'b0),//(w_osm_resp_tx_pulse_p30_osm2hcp),
.i_osm_req_rx_pulse_p31           (1'b0),//(w_osm_req_rx_pulse_p31_osm2hcp ),
.i_osm_resp_tx_pulse_p31          (1'b0) //(w_osm_resp_tx_pulse_p31_osm2hcp)        
); 
/*
mbus_hub mbus_hub_inst
(
        .i_clk                        (i_clk                     ),
        .i_rst_n                      (w_core_rst_n              ),
                                                                 
        .iv_command                   (wv_command_hcp2hub        ),
	    .i_command_wr                 (w_command_wr_hcp2hub      ),
        .ov_command_ack               (wv_command_ack_hub2hcp    ),
        .o_command_ack_wr             (w_command_ack_wr_hub2hcp  ), 
                                                                 
        .iv_command_ack_tse           (wv_command_tse2hub        ),
	    .i_command_ack_wr_tse         (w_command_wr_tse2hub      ),
        .ov_command_tse               (wv_command_hub2tse        ),
        .o_command_wr_tse             (w_command_wr_hub2tse      ),
                                                                 
        .iv_command_ack_tau           (64'b0),//(wv_command_tau2hub        ),
	    .i_command_ack_wr_tau         (1'b0 ),//(w_command_wr_tau2hub      ),
        .ov_command_tau               (     ),//(wv_command_hub2tau        ),
        .o_command_wr_tau             (     ),//(w_command_wr_hub2tau      ),

        .iv_command_ack_frer          (64'b0),//(wv_command_frer2hub        ),
        .i_command_ack_wr_frer        (1'b0 ),//(w_command_wr_frer2hub      ),
        .ov_command_frer              (     ),//(wv_command_hub2frer        ),
        .o_command_wr_frer            (     ),//(w_command_wr_hub2frer      ),
		
        .iv_command_ack_osm_0         (64'b0),//(wv_command_osm2hub_0      ),
	    .i_command_ack_wr_osm_0       (1'b0 ),//(w_command_wr_osm2hub_0    ),
        .ov_command_osm_0             (     ),//(wv_command_hub2osm_0      ),
        .o_command_wr_osm_0           (     ),//(w_command_wr_hub2osm_0    ),
 
        .iv_command_ack_osm_1         (64'b0),//(wv_command_osm2hub_1      ),
	    .i_command_ack_wr_osm_1       (1'b0 ),//(w_command_wr_osm2hub_1    ),
        .ov_command_osm_1             (     ),//(wv_command_hub2osm_1      ),
        .o_command_wr_osm_1           (     ),//(w_command_wr_hub2osm_1    ),
                            
        .iv_command_ack_osm_2         (64'b0),//(wv_command_osm2hub_2      ),
	    .i_command_ack_wr_osm_2       (1'b0 ),//(w_command_wr_osm2hub_2    ),
        .ov_command_osm_2             (     ),//(wv_command_hub2osm_2      ),
        .o_command_wr_osm_2           (     ),//(w_command_wr_hub2osm_2    ), 
                           
        .iv_command_ack_osm_3         (64'b0),//(wv_command_osm2hub_3      ),
	    .i_command_ack_wr_osm_3       (1'b0 ),//(w_command_wr_osm2hub_3    ),
        .ov_command_osm_3             (     ),//(wv_command_hub2osm_3      ),
        .o_command_wr_osm_3           (     ),//(w_command_wr_hub2osm_3    ),
                             
        .iv_command_ack_osm_4         (64'b0),//(wv_command_osm2hub_4      ),
	    .i_command_ack_wr_osm_4       (1'b0 ),//(w_command_wr_osm2hub_4    ),
        .ov_command_osm_4             (     ),//(wv_command_hub2osm_4      ),
        .o_command_wr_osm_4           (     ),//(w_command_wr_hub2osm_4    ), 
                           
        .iv_command_ack_osm_5         (64'b0),//(wv_command_osm2hub_5      ),
	    .i_command_ack_wr_osm_5       (1'b0 ),//(w_command_wr_osm2hub_5    ),
        .ov_command_osm_5             (     ),//(wv_command_hub2osm_5      ),
        .o_command_wr_osm_5           (     ),//(w_command_wr_hub2osm_5    ), 
                           
        .iv_command_ack_osm_6         (64'b0),//(wv_command_osm2hub_6      ),
	    .i_command_ack_wr_osm_6       (1'b0 ),//(w_command_wr_osm2hub_6    ),
        .ov_command_osm_6             (     ),//(wv_command_hub2osm_6      ),
        .o_command_wr_osm_6           (     ),//(w_command_wr_hub2osm_6    ), 
                        
        .iv_command_ack_osm_7         (64'b0),//(wv_command_osm2hub_7      ),
	    .i_command_ack_wr_osm_7       (1'b0 ),//(w_command_wr_osm2hub_7    ),
        .ov_command_osm_7             (     ),//(wv_command_hub2osm_7      ),
        .o_command_wr_osm_7           (     ) //(w_command_wr_hub2osm_7    )     
);
*/
reset_top reset_top_inst(
.i_clk                (i_clk),
.i_rst_n              (w_rst_n),
                      
.i_gmii_rxclk_p0      (i_gmii_rxclk_p0),
.i_gmii_rxclk_p1      (i_clk),//(i_gmii_rxclk_p1),
.i_gmii_rxclk_p2      (i_clk),//(i_gmii_rxclk_p2),
.i_gmii_rxclk_p3      (i_clk),//(i_gmii_rxclk_p3),
.i_gmii_rxclk_host    (i_clk),
                     
.o_core_rst_n         (w_core_rst_n),
.o_gmii_rst_n_p0      (w_gmii_rst_n_p0),
.o_gmii_rst_n_p1      (w_gmii_rst_n_p1),
.o_gmii_rst_n_p2      (w_gmii_rst_n_p2),
.o_gmii_rst_n_p3      (w_gmii_rst_n_p3),
.o_gmii_rst_n_host    (w_gmii_rst_n_p8)
);

reset_clock_check reset_clock_check_inst(
.i_clk            (i_clk          ),
.i_rst_n          (w_core_rst_n   ),

.o_reset_clk_pulse(reset_clk_pulse)  
);
	
time_sensitive_end time_sensitive_end_inst(
.i_clk                    (i_clk                       ),
.i_rst_n                  (w_core_rst_n                ), 

.iv_hcp_mid               (wv_hcp_mid_hcp2tse       ),                          
.i_local_cnt_rst          (w_local_cnt_rst_hcp2osm  ),
.i_tsn_or_tte             (w_tsn_or_tte_hcp2osm     ),
//p0
.i_gmii_rxclk_p0            (i_gmii_rxclk_p0           ),                   
.i_gmii_rst_n_p0          (w_gmii_rst_n_p0           ),             
.i_gmii_rx_dv_p0          (i_gmii_dv_p0              ),
.i_gmii_rx_er_p0          (i_gmii_er_p0              ),
.iv_gmii_rxd_p0           (iv_gmii_rxd_p0            ),
.o_gmii_tx_en_p0          (o_gmii_tx_en_p0           ),
.o_gmii_tx_er_p0          (o_gmii_tx_er_p0           ),
.ov_gmii_txd_p0           (ov_gmii_txd_p0            ),  

.iv_data_host             (iv_data_host  ),
.i_data_wr_host           (i_data_wr_host),
                                         
.ov_data_host             (ov_data_host  ),
.o_data_wr_host           (o_data_wr_host),
      
//p1                                                             
//.i_gmii_rxclk_p1            (i_gmii_rxclk_p1),                       
//.i_gmii_rst_n_p1          (w_gmii_rst_n_p1),                     
//                                                                   
//.i_gmii_rx_dv_p1          (i_gmii_dv_p1   ),                     
//.i_gmii_rx_er_p1          (i_gmii_er_p1   ),                     
//.iv_gmii_rxd_p1           (iv_gmii_rxd_p1 ),                       
//.o_gmii_tx_en_p1          (o_gmii_tx_en_p1),                     
//.o_gmii_tx_er_p1          (o_gmii_tx_er_p1),                       
//.ov_gmii_txd_p1           (ov_gmii_txd_p1 ),                     
//p2                      
//.i_gmii_rxclk_p2            (i_gmii_rxclk_p2),                   
//.i_gmii_rst_n_p2          (w_gmii_rst_n_p2),
//                          
//.i_gmii_rx_dv_p2          (i_gmii_dv_p2   ),
//.i_gmii_rx_er_p2          (i_gmii_er_p2   ),
//.iv_gmii_rxd_p2           (iv_gmii_rxd_p2 ),
//.o_gmii_tx_en_p2          (o_gmii_tx_en_p2),
//.o_gmii_tx_er_p2          (o_gmii_tx_er_p2),
//.ov_gmii_txd_p2           (ov_gmii_txd_p2 ),
//p3                      
//.i_gmii_rxclk_p3            (i_gmii_rxclk_p3),                   
//.i_gmii_rst_n_p3          (w_gmii_rst_n_p3),
//                          
//.i_gmii_rx_dv_p3          (i_gmii_dv_p3  ),
//.i_gmii_rx_er_p3          (i_gmii_er_p3  ),
//.iv_gmii_rxd_p3           (iv_gmii_rxd_p3),
//.o_gmii_tx_en_p3          (o_gmii_tx_en_p3),
//.o_gmii_tx_er_p3          (o_gmii_tx_er_p3),
//.ov_gmii_txd_p3           (ov_gmii_txd_p3 ),
/*
//p4                      
.i_gmii_clk_p4            (i_clk),                   
.i_gmii_rst_n_p4          (w_gmii_rst_n_p4),
                          
.i_gmii_rx_dv_p4          (1'b0 ),
.i_gmii_rx_er_p4          (1'b0 ),
.iv_gmii_rxd_p4           (8'b0  ),
.o_gmii_tx_en_p4          (),//(o_gmii_tx_en_p4),
.o_gmii_tx_er_p4          (),//(o_gmii_tx_er_p4),
.ov_gmii_txd_p4           (),//(ov_gmii_txd_p4 ),
//p5                      
.i_gmii_clk_p5            (i_clk),                   
.i_gmii_rst_n_p5          (w_gmii_rst_n_p5),
                          
.i_gmii_rx_dv_p5          (1'b0  ),
.i_gmii_rx_er_p5          (1'b0  ),
.iv_gmii_rxd_p5           (8'b0  ),
.o_gmii_tx_en_p5          (),//(o_gmii_tx_en_p5),
.o_gmii_tx_er_p5          (),//(o_gmii_tx_er_p5),
.ov_gmii_txd_p5           (),//(ov_gmii_txd_p5 ),
//p6                      
.i_gmii_clk_p6            (i_clk          ),                   
.i_gmii_rst_n_p6          (w_gmii_rst_n_p6),
                          
.i_gmii_rx_dv_p6          (1'b0  ),
.i_gmii_rx_er_p6          (1'b0  ),
.iv_gmii_rxd_p6           (8'b0  ),
.o_gmii_tx_en_p6          (),//(o_gmii_tx_en_p6),
.o_gmii_tx_er_p6          (),//(o_gmii_tx_er_p6),
.ov_gmii_txd_p6           (),//(ov_gmii_txd_p6 ),
//p7                      
.i_gmii_clk_p7            (i_clk          ),                   
.i_gmii_rst_n_p7          (w_gmii_rst_n_p7),
                          
.i_gmii_rx_dv_p7          (1'b0 ),
.i_gmii_rx_er_p7          (1'b0 ),
.iv_gmii_rxd_p7           (8'b0 ),
.o_gmii_tx_en_p7          (),//(o_gmii_tx_en_p7),
.o_gmii_tx_er_p7          (),//(o_gmii_tx_er_p7),
.ov_gmii_txd_p7           (),//(ov_gmii_txd_p7 ),
*/
.o_osm_req_rx_pulse_p0    (w_osm_req_rx_pulse_p0_osm2hcp  ),    
.o_osm_resp_rx_pulse_p0   (w_osm_resp_rx_pulse_p0_osm2hcp ),    
.o_osm_req_tx_pulse_p0    (w_osm_req_tx_pulse_p0_osm2hcp  ),    
.o_osm_resp_tx_pulse_p0   (w_osm_resp_tx_pulse_p0_osm2hcp ),    
     
.o_osm_req_rx_pulse_p1    (w_osm_req_rx_pulse_p1_osm2hcp  ),     
.o_osm_resp_rx_pulse_p1   (w_osm_resp_rx_pulse_p1_osm2hcp ),     
.o_osm_req_tx_pulse_p1    (w_osm_req_tx_pulse_p1_osm2hcp  ),     
.o_osm_resp_tx_pulse_p1   (w_osm_resp_tx_pulse_p1_osm2hcp ),     
     
.o_osm_req_rx_pulse_p2    (w_osm_req_rx_pulse_p2_osm2hcp  ),     
.o_osm_resp_rx_pulse_p2   (w_osm_resp_rx_pulse_p2_osm2hcp ),     
.o_osm_req_tx_pulse_p2    (w_osm_req_tx_pulse_p2_osm2hcp  ),     
.o_osm_resp_tx_pulse_p2   (w_osm_resp_tx_pulse_p2_osm2hcp ),     
     
.o_osm_req_rx_pulse_p3    (w_osm_req_rx_pulse_p3_osm2hcp  ),     
.o_osm_resp_rx_pulse_p3   (w_osm_resp_rx_pulse_p3_osm2hcp ),
.o_osm_req_tx_pulse_p3    (w_osm_req_tx_pulse_p3_osm2hcp  ),
.o_osm_resp_tx_pulse_p3   (w_osm_resp_tx_pulse_p3_osm2hcp ),
                                                            
.i_data_wr_hcp                  (w_data_wr_hcp2tse           ),             
.iv_data_hcp                    (wv_data_hcp2tse             ),                   
.ov_data_hcp                    (wv_data_tse2hcp             ),
.o_data_wr_hcp                  (w_data_wr_tse2hcp        ),

.i_cyclestart                  (o_cyclestart              ),                                 
.ov_tse_ver                     (wv_tse_ver_tse2hcp         ),
.iv_command                     (wv_command_hub2tse         ),      
.i_command_wr                   (w_command_wr_hub2tse       ),      
.ov_command_ack                 (wv_command_tse2hub         ),      
.o_command_ack_wr               (w_command_wr_tse2hub       ),      

.i_rc_rxenable                  (w_rc_rxenable_hcp2tss      ),
.i_st_rxenable                  (w_st_rxenable_hcp2tss      ),

.iv_syn_clk                     (ov_syn_clk),//(wv_syn_clk_stc2swc),
.o_mirror_pkt_wr                ( ),
.ov_mirror_pkt                  ( ),
.o_PTO0                         ( ),
.o_PTO1                         ( ),
.o_PTO2                         ( ),
.o_PTO3                         ( )
                                 
);
endmodule            